Goal:

The goal of this project was to design a 4-1 multiplexer using Complementary Metal Oxide Semiconductor (CMOS) technology, and then verify the design functioned by simulating it in Cadence.


Design:

The multiplexer was designed to select between one of four digital input lines, and forward the input to a single output line. The design was broken into several parts. An inverter was required for the select input. In order to reduce complexity, this design was implemented using three 2-1 multiplexers. The first steps for this design were to derive the functional and logical truth tables, and K-map for the 2-1 multiplexer. The truth tables and K-map for the 2-1 multiplexer are shown below.


Figure 1: 2-1 Multiplexer

Table 1: Functional Truth Table

Table 2: Logical Truth Table

Table 3: K-Map

The circuits designed for this project had two defined parts. The pull-up network was designed with PMOS transistors and the pull-down network was designed with NMOS transistors. The equations shown below were derived using Table 3.

OUTP = (S+A)(S+B)
OUTN = SA + SB

Figure 2 shows the schematic for the pull-up and pull-down network for the 2-1 multiplexer. The stick layout shown in Figure 3 was derived from the schematic shown in Figure 2.

Figure 2: 2-1 Multiplexer Schematic

Figure 3: 2-1 Multiplexer Stick Layout

The 4-1 Multiplexer shown in Figure 4 was implemented using three 2-1 multiplexers. This design was simulated in Cadence. Each multiplexer in this design required an inverter. The design for the inverter is shown in Figure 5.

Figure 4: 4-1 Multiplexer Diagram

Figure 5: Inverter Design 


Simulations:

The multiplexer shown in Figure 6 was implemented using the 2-1 multiplexer design and the inverter design. Three modules were created using the schematic from Figure 6. These modules were then used to implement the 4-1 multiplexer shown in Figure 7. The layout for the 2-1 multiplexer design is shown in Figure 8.

Figure 6: 2-1 Multiplexer Schematic 

Figure 7: 4-1 Multiplexer Schematic 

Figure 8: 2-1 Multiplexer Layout

The simulation results for the 4-1 multiplexer design are shown in Figure 9 and Figure 10. The select inputs S0 and S1 were used to select which input signal was forwarded to the output. D0, D1, D2, and D3 are the input signals. The output signal was compared to the input signal to verify the design functioned correctly.

Finally, the propagation delay of the multiplexer was examined. The propagation delay for input D2 was examined for this project. It was determined that tpLH was 100 picoseconds and tpHL was 80 picoseconds; therefore, tp = (tpHL+tpLH)/2 = (100 picoseconds + 80 picoseconds)/2 = 90 picoseconds. The propagation delay for D2 was determined to be approximately 90 picoseconds. This was very noticeable in the simulation output.

Figure 9: 4-1 Multiplexer Schematic 

Figure 10: 4-1 Multiplexer Schematic 


Summary:

The objective of this project was to design a 4-1 multiplexer using CMOS technology and implement the multiplexer in Cadence. The implementation included a transistor schematic, simulation, and layout.

The design was realized by starting with a functional truth table to understand the operation of the design. Logical truth tables, and k-maps were then used to derive the output equations for the design. The schematics and stick layouts were then drawn out. The designs were then simulated in Cadence.

This project showed how more complex designs could be realized from less complex designs. For example, 2-1 multiplexers were used to implement a 4-1 multiplexer. This project also provided some exposure to the layout process in Cadence.

The propagation delay for one of the inputs was also examined in this project. The propagation delay for D2 was approximately 90 picoseconds. One solution to this problem is to increase the size of the transistor. This would lower the resistance of devices in series and reduce the time constants


References:

www.cs.nyu.edu/courses/fall07/V22.0436-001/diagrams/mux.png